Electronic communications systems commonly rely upon an accurate frequency source or reference clock which typically takes the form of an oscillator. The performance of such systems is dependent upon the accuracy of the oscillator. In digital communications, frequency source inaccuracy tends to result in increased bit error rates. There is, therefore, a continuing need for ever-increasing accuracy of frequency source oscillators.
While an ideal oscillator generates a pure periodic waveform (e.g., a pure sinusoid), practical oscillator signals tend to be noisy including both amplitude noise and phase noise. Phase noise is the phenomenon of random fluctuation in the oscillator phase caused in part by thermal variation. While oscillator phase fluctuations in digital clock generation are usually referred to as “jitter,” the general term “random phase” is commonly used for changes in radio-frequency oscillators.
By way of example, FIG. 1 shows a constellation diagram 100 illustrating the effect of −15 dBc phase noise on a quadrature phase-shift keying (QPSK) signal over additive white Gaussian noise (AWGN) channel with 30 dB signal-to-noise ratio (SNR).
In wireless communications systems characterized by lower data-rate and carrier frequency, phase noise issues do not necessarily cause significant performance degradations. With advances in data-rate, however, and utilization of higher frequency bands (e.g., the 60 GHz ISM band), phase noise issues have become a limiting factor in system performance.
Orthogonal frequency division multiplexing (OFDM) systems have traditionally been used for high data rate wireless communication. Due to OFDM's high sensitivity to phase noise, however, single-carrier (SC) communication with frequency-domain equalization (SC-FDE) is a useful method when transmitting data with high phase noise levels.
Phase noise in SC systems has traditionally been compensated by the use of an analog or digital phase-locked loop (PLL) circuit. A digital PLL (DPLL) circuit can significantly reduce the phase noise levels in low sample rate SC systems. Moreover, DPLL circuits are particularly effective against phase noise in traditional lower carrier frequency wireless systems (e.g., phase noise levels below −25 dBc).
For example, FIG. 2 shows a simplified schematic diagram of a known ideal second order type-II DPLL circuit 200. In this DPLL 200, the estimated phase error is used to predict the future phase error using a second order proportional-integral (PI) controller. FIG. 3 shows a constellation diagram 300 illustrating the effectiveness of the ideal DPLL in compensating the phase noise (wherein a WiGig IEEE 802.11ad system model is used for signal generation).
Effective implementation of a DPLL for phase noise cancellation can be challenging, however. Specifically, sufficient clock cycle budget is required for the DPLL to perform all of its error estimation, PI phase noise prediction, and cancellation. As long as all of the DPLL operations can be performed in one symbol cycle, the DPLL can provide its ideal performance.
By way of example, FIG. 4 shows a simplified schematic diagram of a DPLL circuit 400. The DPLL circuit 400 is similar to the DPLL circuit 200 shown in FIG. 2, but with indicators added illustrating the required clock cycles for each component of the DPLL 400. In each instance, the number of clock cycles required for a particular component in the circuit is designated by D#, where # is the number of clock cycles. In a typical implementation, phase error estimation can be performed in three clock cycles (coordinate rotation digital computer (CORDIC)+modulation slicer), the PI controller would require one clock cycle, complex sine/cosine requires one clock cycle, and a complex multiplication can be performed in one clock cycle. Therefore six clock cycles are required to perform all of the operations of a DPLL. As long as the symbol period is longer than six clock cycles, the DPLL 200 shown in FIG. 2 can effectively reduce the phase noise. This may not be the case, however, in high data rate systems.
For example, in a sample implementation of the IEEE 802.11ad (WiGig) system, the input data arrives at 1760 MS/Sec on a 220 MHz clock, i.e. eight samples per clock cycle. In this case, the effects of the block latencies and symbol period can be modeled in the DPLL as Dtotal=6*8=48 sample delay in the loop as shown in FIG. 4. This total delay is represented figuratively in FIG. 4 as z−Dtotal in block 410. This delay perturbs the DPLL response and significantly reduces its bandwidth hence impairing its effectiveness against the fast changing phase noise as shown in the constellation diagram 500 in FIG. 5.
Several authors have proposed methods for compensating PLL loop delay. See, for example: J. Lee et al., “New phase-locked loop design: understanding the impact of a phase-tracking channel detector,” IEEE Transactions on Magnetics, pp. 830-836, March 2010; S. Ölçer and E. Eleftheriou, “Compensation of PLL Loop Delay in Read Channels for Tape Storage Systems,” In proceedings of GLOBECOM '09, pp. 1-5, December 2009; and A. Patapoutian, “Loop latency compensated PLL filter,” U.S. Pat. No. 6,236,343 B1, May 2001. These references propose compensating the PLL loop response by introducing extra delay in the PLL loop in various forms. This extra delay slows down the PLL response, however, and reduces the PLL's ability to track fast-changing phase noise making it even less effective.
Further proposed methods which do not overcome all of the disadvantages described above are taught in United States Patent Application Publication No. US 2012/0155890 A1, U.S. Pat. No. 8,258,877, and WIPO International Patent Publication No. WO 2000/070767.
There remains a need, therefore, for an effective method to compensate for phase noise distortions in high sample rate communication systems. The method should be robust enough to work effectively with the circuit delays necessary to make ASIC implementation feasible.
Moreover, automatic gain control (AGC) functionality is required in communication systems for correct de-mapping of the received samples. It would be advantageous for AGC operation to be paired with phase noise and residual frequency offset compensation for improved performance and reduced complexity.